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KT8555
TIME SLOT ASSIGNMENT CIRCUIT
INTRODUCTION
20-CERDIP The KT8555 is a per channel Time Slot Assignment Circuit (TSAC) that produces 8-bit receive and transmit time slots for four 1 CHIP CODEC. Each frame synchronization pulse may be independently assigned to a time slot in a frame of up to 84 time slots.
FEATURES
l l l l l l l l Single, 5V operation Low power consumption: 5mW Controls four 1 CHIP CODEC Independent transmit and receive frame syncs enables channel unidirectional mode Up to 64 time slots per frame Compatible with KT8554/7 CODECs TTL and CMOS compatible
ORDERING INFORMATION
Device KT8555J Package 20-CERDIP Operating Temperature - 20C ~ + 125C
PIN CONFIGURATION
FSX1 FSR1 FSX0 FSR0 TSX DC CLKC CS MODE
1 2 3 4 5 6 7 8 9
20 VCC 19 FSR2 18 FSX2 17 FSR3 16 FSX3 15 CH0 14 CH1 13 RSYC/CH2 12 XSYC 11 BCLK
KT8555
GND 10
Fig. 1
KT8555
PIN DESCRIPTION
Pin No 3 1 18 16 4 2 19 17 5 6 7 8 9 10 11 12 Symbol FSX0 FSX1 FSX2 FSX3 FSR0 FSR1 FSR2 FSR3 TSX DC CLKC CS MODE GND BCLK XSYC
TIME SLOT ASSIGNMENT CIRCUIT
Description A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made.
A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made.
This pin pulls low during any active transmit time slot. (N-channel open drain) The input for an 8 bit serial control word. X is the first bit clocked in. The clock input for the control interface. The active-low chip select for the control interface. Mode 1 = Open or VCC Mode 2 = Gnd Ground The bit clock input (2.048 MHz) The transmit TSO sync pulse input. Must be synchronous with BCLK. The transmit time slot 0 sync pulse input. Must be synchronous with BCLK.
13
RSYC /CH2
In mode 1 this input is the receive time slot 0 sync pulse, RSYC, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word.
14 15 20
CH1 CH0 VCC
The input for the NSB (next significant bit) of the channel select word. The input for the LSB (last significant bit) of the channel select word, which defines the frame sync output affected by the following control word. Power supply pin. 5V 5%
ABSOLUTE MAXIMUM RATINGS
Characteristic Positive Supply Voltage Input Voltage Output Voltage Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 secs)
(Ta = 25C) Symbol VCC VI VO T OPR T STG T LEAD Value 7.0 VCC + 0.3 ~ - 0.3 VCC + 0.3 ~ - 0.3 - 25 ~ 125 - 65 ~ 150 300 Unit V V V C C C
KT8555
ELECTRICAL CHARACTERISTICS
Characteristic Operating Current Input Voltage High Input Voltage Low Input Current 1 Input Current 2 Output Voltage High Output Voltage Low Rise and Fall Time of Clock Delay to TSX Low Delay to TSX High Hold Time from BCLK to Frame Sync Set-Up Time from Frame Sync to BLCK Delay Time from BLCK Low to FXX/R 0-3 High or Low Hold Time from Channel Select to CLKC Set-Up Time from Channel Select to CLKC Period of Clock Width of Clock High Width of Clock Low Set-Up Time from DC to CLKC Hold Time from CLKC to DC Set-Up Time from CS to CLKC Hold Time from CLKC to CS
TIME SLOT ASSIGNMENT CIRCUIT
(Unless otherwise noted; VCC = 5.0V 5%, Ta = 0C ~70C) Symbol ICC VIH VIL II1 II2 VOH VOL tR (CK) tF(CK) tD (TSX L) tD (TSX H) tH (BFS) tH (FSB) tD tH (CSC) tSU (CSC) tCK tW (CKH) tW (CLK) tSU (Dc C) tH (CDc) tSU (CC) tH (CC) BCLK, CLKC BCLK, CLKC BCLK, CLKC CL = 50pF 50 30 240 50 50 30 50 30 100 All Inputs Except Mode, VILTIMING DIAGRAM
tHCD tW(CKH) tW(CKL) CONTROL INTERFACE tH(CC) CLK C tR(CK) tF(CK) tSU(CC)
tH(CC)
CS tSU(CC) CH0, CH1 AND CH2 tSU(DcC) DC 1 2 tWCH tSU(FSB) BCLK tH(BFS) tRS XSYC OR RSY C tD FS X OR FS R tD(TSxH) MIN tD(TSxH) MAX TS X tFS tF(CK) 1 tDT(SxL) 2 tW(CKL) tR(CK) tD 3 4 5 6 7 8 3 4 OUTPUT 5 6 7 tH(CSC) 8 tSU(CSC)
KT8555
APPLICATION INFORMATION OPERATING CONTROL MODE 1
TIME SLOT ASSIGNMENT CIRCUIT
The KT8555 is a control interface which requires an 8 bit serial control word. Either one of the frame sync output group, FSX0 to FXX3 or FSR0 to FSR3, affected by the control word is defined by the two bits, X and R. Time slot selected from 0 to 63 is specified. A frame sync output is highly active for one time slot which is equivalent to 8 cycles of BCLK. Up to 64 time slots are allowed to form a frame. There are two operational mode. In mode 1, each channel of transmit and receive direction has different time slot assigned. This mode can be selected by either leaving pin 9 (MODE) opened or connecting it with VCC. In such a case, pin 13 is RSYC input defining the start of each receive frame while four output, FSR0 to FSR3, are assigned with respect to RSYC. On the other hand, start of each transmit frame is defined by XSYC input by which output FSX0 to FSX3, are assigned. XSYC and RSYC can be phase related. Channels from 0-3 are selected by the input CH0 and CH1 (refer to the table 1). X R T5 T4 T3 T2 T1 T0 CH1 0 0 1 1 CH0 0 1 0 1 Channel Selected Assign to FSX0 and/or FSR0 Assign to FSX1 and/or FSR1 Assign to FSX2 and/or FSR2 Assign to FSX3 and/or FSR3
X is the first bit clocked into DC input
CONTROL DATA FORMAT T5 0 0 0 T4 0 0 0 T3 0 0 0 T2 0 0 0 T1 0 0 1 T1 0 1 0 Time Slot 0 1 2 . . . 30 31 32 33 . . . 63 X 0 0 1 1 R 0 1 0 1 Action Assign time slot to both selected FSX and FSR Assign time slot to selected FSX only Assign time slot to selected FSR only Disable both selected FSX and FSR
0 0 1 1
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
0 1 0 1
1
1
1
1
1
1
TABLE 1. OPERATING CONTROL MODE 1
OPERATING CONTROL MODE 2
In mode 2, all 8 frame sync outputs can be assigned with respect to XSYC input. The mode 2, selected by connecting pin 9 (MODE) to GND, enables the KT8555 TSAC suitable for an 8-channel unidirectional controller and for a system where both transmit and receive direction of each channel have same time slot assigned. For instance, FSX and FSR input of 1 CHIP CODEC are hard wired together. The channel assigned has its channel selected by CH0, CH1 and CH2 (refer to table 2). CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 Channel Selected Assign to FSX0 Assign to FSX1 Assign to FSX2 Assign to FSX3 Assign to FSR0 Assign to FSR1 Assign to FSR2 Assign to FSR3 X 0 0 1 1 R 0 1 0 1 Action Assign time slot to selected output Assign time slot to selected output Assign time slot to selected output Disable both selected output
TABLE 2. OPERATING CONTROL MODE 2
KT8555
APPLICATION CIRCUIT
TIME SLOT ASSIGNMENT CIRCUIT
The KT8555 TSAC combined with any kind of 1 CHIP CODEC from KT8554/7 series can obtain data timing as illustrated in Fig. 3. Even though FSX output goes high before BCLK gets high, the DX output of the 1 CHIP CODEC remains in the TRI-STATE mode until both outputs are high. The eight bit period is shortened to avoid PCM data clash at PCM prehighway. Alternatively, full 8 bits can be obtained by inverting the BCLK to the 1 CHIP CODEC devices, thereby rising edges of BCLK and FSX/R are aligned. Fig. 4 is typical timing of the control data interface. Fig. 5 is the typical application circuit at operating control mode 2.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
BCLK
XSYC
FS X 1
FS X 2
DX
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
TS X
Fig. 3 Transmit Data Timing
CLKC
CH0, CH1
CS
DC
X
R
T5
T4
T3
T2
T1
T0
X
R
T5
T4
Fig. 4 Control Data Timing
TIME SLOT ASSIGNMENT CIRCUIT
13 TS X 7 CLKSEL 10 BCLKX 9 MCLKX +5V 6 DR 12 10 9 GND MODE FSX0 FSX1 FSX2 18 1 3 5 FSX FSR 0.1F
VFXI+ 16
VFXI- 15
KT8554/57
GSX DX VFRO PDN 14 11 3 8
20 VCC
CH0 CH1 CH2 CS
KT8555
8 CS 7 CLKC 11 BCLK 12 XSYC 6 DC 13 CH2 FSX3 16 FSR0 FSR1 4 2 FSR2 19 FSR3 17 14 CH1
15 CH0
1 CHIP CODEC #1 1 CHIP CODEC #2 1 CHIP CODEC #3 1 CHIP CODEC #4 1 CHIP CODEC #5 1 CHIP CODEC #6
CLKC BCLK XSYC DC
5 FSR
PDN 12 FSX
8 VFRO 3 6 DR DX 11
MSB X R T5 T3 T2 T4
LSB T1 T0
NOTE 2 : X, R action status X 0 0 1 1 1 1 0 R 0 Action Timesolt assign Time slot assign Time slot assign Time slot assign disable
KT8554/57
9 MCLK X 10 BCLKX 7 CLKSEL 13 TSX
GSX
14
VFXI+ 16
1 CHIP CODEC #7 NOTE 4 : Time slot assign status Time Slot T4 T3 T2 T1 T0 0 1 2 . . . . 62 63
NOTE 3 : T5 action status T5 0 1 Action Normal operation Time slot assign disable
KT8555
0 0 0 . . . . 1 1
0 0 0 . . . . 1 1
0 0 0 . . . . 1 1
0 0 1 . . . . 1 1
0 1 0 . . . . 0 1
respectively also available.
VFXI- 15
NOTE 5 : Different time slot assign for RX and TX
NOTE 1 : Dc Format
Fig. 5 Digital interface on a typical subscriber linecard
1 CHIP CODEC # 0

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